HeteroPar will be held on August 23, 2022 (full day workshop) at the University of Glasgow, UK (collocated with Euro-Par 2022).
KEYNOTE : It is our great pleasure to announce Prof. Paul Kelly from Imperial College London as a special keynote speaker at HeteroPar'22. More details can be found at the keynote page.
PROGRAM / EVENT : Full program of the HeteroPar'22 workshop is available here. HeteroPar will be primarily in-person event, but some provisions to present, attend and interact online will also be provided.
REGISTRATION / AUTHOR INFO : Please consult the Euro-Par'22 registration page for details on how to register to attend the workshop. Additional information for the authors of accepted papers can also be found here.
The 20th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 2022) will be held on August 23, 2022 as a full-day workshop at the University of Glasgow, Scotland, United Kingdom.
For the 13th time, HeteroPar is organized in conjunction with the Euro-Par annual series of international conferences dedicated to the promotion and advancement of all aspects of parallel computing.
Heterogeneity is emerging as one of the most profound and challenging characteristics of today's parallel environments. From the macro level, where networks of distributed computers, composed of diverse node architectures, are interconnected with potentially heterogeneous networks, to the micro level, where deeper memory hierarchies and various accelerator architectures are increasingly common, the impact of heterogeneity on all computing tasks is increasing rapidly. Traditional parallel algorithms, programming environments and tools, designed for legacy homogeneous multiprocessors, will at best achieve a small fraction of the efficiency and the potential performance that we should expect from parallel computing in tomorrow's highly diversified and mixed environments. New ideas, innovative algorithms, and specialized programming environments and tools are needed to efficiently use these new and multifarious parallel architectures. The workshop is intended to be a forum for researchers working on algorithms, programming languages, tools, and theoretical models aimed at efficiently solving problems on heterogeneous platforms.
Topics to be covered include but are not limited to:
Heterogeneous parallel programming paradigms and models
Languages, libraries, and interfaces for heterogeneous parallel programming models
Performance models and their integration into the design of efficient parallel algorithms for heterogeneous platforms
Parallel algorithms and scheduling for heterogeneous and/or hierarchical systems, including manycores and hardware accelerators (e.g. FPGAs, GPUs, AI accelerators)
Parallel algorithms for efficient problem solving on heterogeneous platforms (e.g. numeri- cal linear algebra, nonlinear systems, fast transforms, computational biology, data mining, artificial intelligence, multimedia)
Applications and software engineering for heterogeneous parallel systems
Algorithms, models and tools for energy and/or multi-objective optimization on heterogeneous platforms
Integration of parallel and distributed computing on heterogeneous systems
Experience of porting parallel software from supercomputers to heterogeneous platforms
Fault tolerance of parallel computations on heterogeneous platforms
Algorithms, models and tools for grid, desktop grid, cloud, and green computing that include heterogeneous computing aspect
Authors are encouraged to submit original, unpublished research or overviews on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms, namely addressing the topics referred above.
|09:00 - 09:10||Opening note|
|09:10 - 10:00||KEYNOTE: "Domain-specific compiler architecture for today’s accelerators and tomorrow’s"
Imperial College London, UK
|10:00 - 10:30||"Programming Heterogeneous Architectures Using Hierarchical Tasks"
M. Faverge, N. Furmento, A. Guermouche, Gwenolé Lucas, R. Namyst, S. Thibault and P.-A. Wacrenier
Inria Bordeaux Sud-Ouest, France
|11:00 - 11:30||"A C++ library for memory layout and performance portability of scientific applications"
Pietro Incardona, A. Gupta, S. Yaskovets and I. Sbalzarini
TU Dresden / Max Planck Institute of Molecular Cell Biology and Genetics / Center for Systems Biology Dresden / ScaDS.AI, Dresden/Leipzig, Germany
|11:30 - 12:00||"Implementation and Performance Evaluation of Memory System using Addressable Cache for HPC applications on HBM2 equipped FPGAs"
Norihisa Fujita, R. Kobayashi, Y. Yamaguchi and T. Boku
Center for Computational Sciences, University of Tsukuba, Japan
|12:00 - 12:30||"Programming abstractions for preemptive scheduling in FPGAs using partial reconfiguration"
Gabriel Rodriguez-Canal, N. Brown, Y. Torres and A. Gonzalez-Escribano
EPCC, The University of Edinburgh, UK / Escuela de Ingeniería Informática at Universidad de Valladolid, Spain
|14:00 - 14:30||"Modeling Task Mapping for Data-intensive Applications in Heterogeneous Systems"
Martin Wilhelm, H. Geppert, A. Drewes and T. Pionteck
Otto-von-Guericke University, Magdeburg, Germany
|14:30 - 15:00||"Mapping Tree-shaped Workflows on Memory-heterogeneous Architectures"
Svetlana Kulagina, H. Meyerhenke and A. Benoit
Department of Computer Science, Humboldt-Universitat zu Berlin, Germany / LIP laboratory, ENS Lyon, France
|15:00 - 15:30||"Hetero-Vis: A Framework for Latency Optimized Deployment of Convolutional Neural Networks on Heterogeneous Architectures"
Nupur Sumeet, K. Rawat, M. Nambiar and R. Singhal
Tata Consultancy Services, India
|16:00 - 16:30||"Rapid development of OS support with PMCSched for scheduling on asymmetric multicore systems"
C. Bilbao, Juan Carlos Saez and M. Prieto-Matias
Facultad de Informática, Universidad Complutense de Madrid, Spain
|16:30 - 17:00||"HIPLZ: Enabling Performance Portability for Exascale Systems"
Jisheng Zhao, C. Bertoni, J. Young, K. Harms, V. Sarkar and B. Videau
Georgia Institute of Technology, Atlanta, GA / Argonne National Laboratory, Lemont, IL
|17:00 - 17:30||"StorAlloc: A Simulator for Job Scheduling on Heterogeneous Storage Resources"
Julien Monniot, F. Tessier, M. Robert and G. Antoniu
|17:30 - 18:00||"Performance and scalability analysis of AI-accelerated CFD simulations across various computing platforms"
Krzysztof Rojek and R. Wyrzykowski
Dept. Computer Science, Czestochowa University of Technology, Poland
Imperial College London, UK
Title: Domain-specific compiler architecture for today’s accelerators and tomorrow’s
Abstract: Domain-specific languages enable the compiler to understand more about what you are trying to do. If we get it right, DSLs enable us, at the same time, both to boost programmer productivity and also to automate sophisticated domain-specific optimisations that would be hard to do by hand - yet are essential to achieving efficient use of the hardware. DSLs are power tools for performance programming - and for effective exploitation of accelerators. This talk will offer some of our experience in building DSLs that deliver productivity, performance and performance portability. DSLs enable us to find the right representation for a program so that complex optimisations turn out to be easy – so DSLs demand that we pay attention to compiler “architecture”. I will try to map out how to design domain-specific compiler architecture – and set out a vision for a future where we work together to build on representations that are common across different DSLs, and which support the growing diversity of high-performance hardware available.
Short bio: Paul Kelly leads the Software Performance Optimisation group at Imperial College London. His research focus is domain-specific program optimisation, leading to close engagement with colleagues in computational science, robotics and computer vision. This talk covers joint work with many such collaborators.
Authors notification: July 01, 2022
Submission Guidelines: Authors are invited to submit papers electronically, through EasyChair. The papers should be submitted in PDF, following the Springer LNCS format . Paper length must not exceed 12 pages (including references). All submitted manuscripts will be checked for originality by Springer iThenticate (papers that show an insufficient originality might be rejected without a review).
Workshop Proceedings: Accepted papers that are presented at the workshop, will be published in a revised form in a special Euro-Par Workshop Volume in the Lecture Notes in Computer Science (LNCS) series after the Euro-Par conference.
Journal Special Issue: Authors of selected papers accepted for presentation at HeteroPar'2022 will be invited to submit a revised and extended version of their work to a special issue of Wiley's Concurrency and Computation Practice and Experience journal.
INESC-ID, Instituto Superior Técnico
University of Lisbon